Nonvolatile memory devices such as flash memory devices, are capable of preserving data stored in a memory cell even when power is not supplied. Flash memory devices are also capable of high-speed electric erasing of the data in a state of being mounted to a circuit board. An electrically erasable programmable read-only memory (EEPROM) is a nonvolatile memory device which is electrically rewritable. An EEPROM may have a general structure that includes a floating gate cell. In accordance with increased demand to manufacture highly integrated semiconductor devices, it is very desirable to reduce the size of the floating gate cell. However, because high voltage is required when performing programming and erasing and a predetermined space is required to define a tunnel, it is very difficult to accomplish further reduction of the floating gate type cell. Consequently, research has been actively conducted into non-volatile memory devices such as polysilicon-oxide-nitride-oxide-semiconductor (SONOS), ferro-electric random-access memory (FeRAM), single-electron transistor (SET), non-volatile read-only memory (NROM) etc., as substitutes for the floating gate cell. Among them, the SONOS cell is attracting public attention as a next generation cell that can substitute for the floating gate cell.
As illustrated in example FIG. 1A, a fabrication process of an embedded memory device may include forming field oxide layer 2 in semiconductor substrate 1 through a shallow trench isolation (STI) process, thereby defining a field area and an active area. Semiconductor substrate 1 in the active area is separated by field oxide layer 2 into a logic P-type metal oxide semiconductor (PMOS) area, a logic N-type metal oxide semiconductor (NMOS) area, and a logic memory area.
As illustrated in example FIG. 1B, a tunneling oxide layer, a trap nitride layer, and a block oxide layer are deposited sequentially on and/or over semiconductor substrate 1, thereby forming coupling oxide layer 3. Coupling oxide layer 3 may generally refer to all layers fabricated in a manner that the tunneling oxide layer, the trap nitride layer and the block oxide layer are sequentially deposited and patterned. An annealing process is performed at about 800 to 950° C. to enhance the quality of coupling oxide layer 3. Coupling oxide layer 3 may be formed by patterning the block oxide layer so that the block oxide layer remains at only a portion of the memory area to form coupling oxide layer 3. A wet etching process which uses a H3PO4 solution as a mask is then performed on the patterned block oxide layer, thereby removing the trap nitride layer. A flash high voltage (FHV) oxide layer for forming an FHV transistor of a charge pumping circuit may then be formed in order to apply high voltage to the memory device formed on the tunneling oxide layer exposed by removal of the trap nitride layer. Additionally, ion implantation for forming a well is performed so that a P-well is formed in the logic NMOS area. An N-well may be formed in the logic PMOS area and the memory area. The memory device is the PMOS memory, and the N-well is formed. When forming the PMOS memory, the N-well may be formed in the memory area. Then, the FHV oxide layer remaining on and/or over the area except the charge pumping circuit area is removed. The FHV oxide layer formed on and/or over the NMOS area, the PMOS area and the memory area is all removed. After etching the tunneling oxide layer by using the block oxide layer as a mask, a gate oxide layer may then be formed on and/or over semiconductor substrate 1 exposed by the removal of the tunneling oxide layer.
As illustrated in example FIG. 1C, a polysilicon layer is applied to the whole surface of semiconductor substrate 1 and then selectively removed, such that a PMOS gate is formed on and/or over the PMOS area and an NMOS gate is formed on and/or over the NMOS area. Control gate 4 is formed on and/or over coupling oxide layer 3 in the logic memory area.
As illustrated in example FIG. 1D, a lightly doped drain (LDD) area is formed by implanting low-concentration dopant ions using the respective gates as masks. Insulating sidewall 5 is formed at both sides of the respective gates. Using the respective gates and sidewalls 5 of the insulating layer as masks, high-concentration dopant ions are implanted, thereby forming a high-concentration dopant area. Through the fabrication processes for a logic CMOS device as described above, the logic embedded memory device is completed.
However, in the above-described logic embedded memory device, each device has a large size, and density among the respective memory devices is great. Therefore, the logic embedded memory device is restricted in use as a large-capacity memory. When the size of the memory device is reduced so as to decrease the density among the memory devices, due to the above problem, a coupling ratio of the respective memory devices is reduced. As a result, the property of the memory device is deteriorated.